The present invention relates generally to flash memory technology, and more particularly, to a method for fabricating a self-aligned flash memory cell with dimensions that are beyond photolithography limitations and with minimized bit line to bit line leakage current and with maximized area of drain and source bit line silicides.
Referring to FIG. 1, a flash memory cell 100 of a flash memory device includes a tunnel dielectric structure 102 typically comprised of silicon dioxide (SiO2) as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure 102 is disposed on a semiconductor substrate or a p-well 103. In addition, a floating gate structure 104, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure 102. A floating dielectric structure 106, typically comprised of silicon dioxide (SiO2), is disposed over the floating gate structure 104. A control gate structure 108, comprised of a conductive material, is disposed over the floating dielectric structure 106.
A drain bit line junction 110 that is doped with a bit line dopant, such as arsenic (As) or phosphorous (P) for example, is formed within an active device area 112 of the semiconductor substrate or p-well 103 toward a left sidewall of the tunnel dielectric structure 102 in FIG. 1. A source bit line junction 114 that is doped with the bit line dopant is formed within the active device area 112 of the semiconductor substrate or p-well 103 toward a right sidewall of the tunnel dielectric structure 102 of FIG. 1.
During the program or erase operations of the flash memory cell 100 of FIG. 1, charge carriers are injected into or tunneled out of the floating gate structure 104. Such variation of the amount of charge carriers within the floating gate structure 104 alters the threshold voltage of the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate structure 104, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are tunneled out of the floating gate structure 104, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell 100, as known to one of ordinary skill in the art of electronics.
During programming of the flash memory cell 100 for example, a voltage of +9 Volts is applied on the control gate structure 108, a voltage of +5 Volts is applied on the drain bit line junction 110, and a voltage of 0 Volts is applied on the source bit line junction 114 and on the semiconductor substrate or p-well 103. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are injected into the floating gate structure 104 to increase the threshold voltage of the flash memory cell 100 during programming of the flash memory cell 100.
Alternatively, during erasing of the flash memory cell 100, a voltage of xe2x88x929.5 Volts is applied on the control gate structure 108, the drain bit line is floated at junction 110, and a voltage of +4.5 Volts is applied on the source bit line junction 114 and on the semiconductor substrate or p-well 103 for example. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are pulled out of the floating gate structure 104 to decrease the threshold voltage of the flash memory cell 100 during erasing of the flash memory cell 100. Such an erase operation is referred to as an edge erase process by one of ordinary skill in the art of flash memory technology.
In an alternative channel erase process, a voltage of xe2x88x929.5 Volts is applied on the control gate structure 108 and a voltage of +9 Volts is applied on the semiconductor substrate or p-well 103 with the drain and source bit line junctions 110 and 114 floating. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are pulled out of the floating gate structure 104 to the substrate or p-well 103 to decrease the threshold voltage of the flash memory cell 100 during erasing of the flash memory cell 100.
The tunnel dielectric structure 102, the floating gate structure 104, the floating dielectric structure 106, and the control gate structure 108 comprise the gate structure of the flash memory cell 100. Such structures and operation of the flash memory cell 100, are known to one of ordinary skill in the art of flash memory technology.
Referring to FIG. 2, in the prior art, for forming the gate structure of the flash memory cell 100, a layer of tunnel dielectric material 122, comprised of silicon dioxide (SiO2) for example, is deposited on the semiconductor substrate 103. In addition, a layer of floating gate material 124, comprised of polysilicon for example, is deposited on the layer of tunnel dielectric material 122, and a layer of floating dielectric material 126, comprised of silicon dioxide (SiO2) for example, is deposited on the layer of floating gate material 124. Furthermore, a layer of control gate material 128, comprised of polysilicon for example, is deposited on the layer of floating dielectric material 126.
Referring to FIGS. 2 and 3, a photoresist structure 130 comprised of photoresist material is patterned on the layer of control gate material 128. Referring to FIG. 3, any portions of the layer of control gate material 128 not under the photoresist structure 130 is etched away to form the control gate structure 108 comprised of the control gate material remaining under the photoresist structure 130. Similarly, any portions of the layer of floating dielectric material 126 not under the photoresist structure 130 is etched away to form the floating dielectric structure 106 comprised of the floating dielectric material remaining under the photoresist structure 130. In addition, any portions of the layer of floating gate material 124 not under the photoresist structure 130 is etched away to form the floating gate structure 104 comprised of the floating gate material remaining under the photoresist structure 130. Furthermore, any portions of the layer of tunnel dielectric material 122 not under the photoresist structure 130 is etched away to form the tunnel dielectric structure 102 comprised of the tunnel dielectric material remaining under the photoresist structure 130.
Processes for deposition and patterning of the layer of tunnel dielectric material 122, the layer of floating gate material 124, the layer of floating dielectric material 126, and the layer of control gate material 128, with the photoresist structure 130 to form the gate structure comprised of the tunnel dielectric structure 102, the floating gate structure 104, the floating dielectric structure 106, and the control gate structure 108, are known to one of ordinary skill in the art of flash memory technology.
Referring to FIGS. 3 and 4, after such patterning of the gate structure comprised of the tunnel dielectric structure 102, the floating gate structure 104, the floating dielectric structure 106, and the control gate structure 108, the photoresist structure 130 is etched away. In addition, a bit line dopant, such as phosphorous or arsenic for an N-type dopant, is implanted into exposed regions of the active device area of the semiconductor wafer 103 to form the drain bit line junction 110 and the source bit line junction 114. Such an implantation process for formation of the drain and source bit line junctions 110 and 114 is known to one of ordinary skill in the art of flash memory technology.
Then, spacers 132, comprised of a dielectric material such as silicon dioxide (SiO2) for example, are formed on the sidewalls of the gate structure of the flash memory cell. Then, a drain bit line silicide 134 is formed with an exposed region of the drain bit line junction 110 for providing low resistance contact to the drain bit line junction 110, and a source bit line silicide 136 is formed with an exposed region of the source bit line junction 114 for providing low resistance contact to the source bit line junction 114. Processes for formation of such spacers 132 and such drain and source bit line silicides 134 and 136 are known to one of ordinary skill in the art of flash memory technology.
With steps of fabrication of the flash memory cell illustrated in FIGS. 2, 3, 4, and 5, according to the prior art, the minimum length of the gate structure for defining the channel length 138 of the flash memory cell between the drain and source bit line junctions 110 and 114 is limited by photolithography limitations. However, such a channel length dimension is desired to be scaled down further for enhancing the speed performance of the flash memory cell. In addition, referring to FIG. 5, the area of the drain and source bit line silicides 134 and 136 is decreased by formation of the spacers 132 on the drain and source bit line junctions 110 and 114. However, a maximized area of the drain and source bit line silicides 134 and 136 is desired for minimizing parasitic resistance at the drain and source bit lines of the flash memory cell.
Accordingly, in a general aspect of the present invention, spacers and a self-aligned gate structure of a flash memory cell are formed within a gate opening for fabricating the flash memory cell with a channel length dimension that is beyond photolithography limitations and with minimized bit line to bit line leakage current and with maximized area of drain and source bit line silicides.
In a general aspect of the present invention, for fabricating a flash memory cell, a dummy gate structure is formed on an active device area of a semiconductor substrate. A drain bit line junction is formed within the active device area of the semiconductor substrate to a first side of the dummy gate structure, and a source bit line junction is formed within the active device area of the semiconductor substrate to a second side of the dummy gate structure. A drain bit line silicide is formed within the drain bit line junction, and a source bit line silicide is formed within the source bit line junction.
Furthermore, an interlevel material is formed to surround the dummy gate structure, and the dummy gate structure is then etched away to form a gate opening within the interlevel material. Spacers are then formed at sidewalls of the gate opening within the gate opening. After formation of the spacers, a tunnel dielectric structure is formed at a bottom wall of the gate opening, and a floating gate structure is formed on the tunnel dielectric structure within the gate opening. In addition, a floating dielectric structure is formed on the floating gate structure within the gate opening, and a control gate structure is formed on the floating dielectric structure within the gate opening.
In this manner, a self-aligned gate structure is formed to be comprised of the tunnel dielectric structure, the floating gate structure, the floating dielectric structure, and the control gate structure between the spacers within the gate opening. Additionally, because the drain and source bit line silicides are formed before formation of the spacers, the area of the drain and source bit line silicides is not limited by formation of the spacers to maximize the area of the drain and source bit line silicides. In addition, because the spacers are formed before the self-aligned gate structure, the channel length of the flash memory cell defined by the length of the self-aligned gate structure is further decreased by the width of the spacers such that the channel length of the flash memory cell may be reduced beyond that possible from photolithography limitations. Furthermore, because the drain and source bit line junctions are formed with the dummy gate structure that has a longer length than the length of the selfaligned gate structure, the distance between the drain and source bit line junctions is maximized to minimize the leakage current between the drain bit line junction and the source bit line junction.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.